1. Field of the Invention
The present invention relates to a pulse generating device, and, more particularly, to a pulse generating device capable of generating a pulse signal for driving a power switch device in accordance with pulse generation data or the like transmitted from a CPU, to a microcomputer employing the above-described pulse generating device and to a contents addressable memory for use in the above-described devices.
2. Description of the Related Art
A PWM (Pulse Width Modulation) pulse generating device has been used to control voltage to be applied to a variety of devices. For example, it acts as a device for converting supplied voltage data, which has been calculated by a CPU, into a signal for driving a power switch device of a PWM inverter.
Conventional devices of the type described above have been disclosed in Japanese Patent Laid-Open No. 59-113792, Japanese Patent Laid-Open No. 61-116994, Japanese Patent Publication No. 60-2510, Japanese Patent Publication No. 63-18018 and Japanese Patent Laid-Open No. 62-163579. Furthermore, a device is known which is included in a microcomputer (Product No. i8096) manufactured by Inkel, U.S.A. and another device included in a microcomputer (Product No. HD6475328) manufactured by Hitachi.
According to the above-described conventional technology, there has been a PWM pulse generating device having a plurality of interval timers and a plurality of registers. The PWM pulse generating device acts to compare time data which defines the pulse width set to each of the registers with the value of the interval timer so as to change the binary status of the corresponding PWM pulse at timing at which they coincide with each other. Another PWM pulse generating device has been known which comprises a contents addressable memory which is structured in such a manner that the time at which the binary status of the free-run timer is changed is arranged to be a tag, the binary status after the above-described change is arranged to be data and the value of the free-run timer is arranged to serve as a retrieval key. According to this technology, the value of the free-run timer and all of the tags are subjected to comparisons in the contents addressable memory. Then, data corresponding to the coincident tags is arranged to be transmitted.
However, there arises a problem in that an error takes place in the pulse width due to the timing at which the value of the register, which defines the width of the PWM pulse, is reloaded. What is even worse, an excessively large load is applied to the CPU since writing to the register must be performed whenever the time data or the like of the PWM pulse is changed.
A device using the free-run timer must be arranged in such a manner that the first transition time of the PWM pulse and the last transition time of the same are instructed at each period of the PWM carrier. Since the time instruction of the type described above enlarges the load to be applied to the CPU, the throughput in the calculation process performed by the CPU is deteriorated. For example, at least 24 data items must be generated and transferred in a bridge type three-phase inverter for controlling the rotation of an electric motor since gate pulses for switching devices for phase U, phase V and phase W.times.6 arms must be generated.
The upper arm and the lower arm of the bridge structure which are complementarily turned on/off. In order to prevent a short cut of the upper arm and the lower arm, a pair of gate pulses which correspond to the upper arm and the lower arm respectively have a dead time in which both of the arms are turned off.
However, since the above-described conventional technology has no means to reduce the number of data items to be transferred at the time of generating the pulses, a problem arises in that an excessively large load can be applied to the CPU at the time of the data transference. In particular, if a carrier wave having higher frequency is desired in the pulse width modulation (PWM) control operation, an excessively large load is applied at the transference process.
Similarly, another problem arises in the process of calculating the above-described dead time that the load to be applied to the CPU becomes too large when higher frequency wave is obtained.
It might therefore be feasible to employ a method in which an interval timer is used as an alternative to the free-run timer and the necessity of time instruction is eliminated in a period in which the PWM signal has a predetermined waveform. However, in a case where the value of the tag has been reloaded to a value which is smaller than the value of the interval timer, the tag and the retrieval key cannot coincide with each other in the PWM period in which the value is reloaded, causing a fear to be arisen in that an error can be generated in the pulse width.